The present invention relates to a computational circuit, and more specifically, to a squaring circuit using a MOS or MIS transistor.
Hitherto, MOS transistors are exclusively employed in digital circuits using digital signals "0" and "1". On the other hand, recently, it has been increasingly desired for the MOS transistor to handle analog signals. For example, a squaring circuit is required for a full wave rectification of a small alternating-current signal. In this case, if the signal is digitally processed, it is necessary to employ an AD converter circuit, a digital squaring circuit, and a DA converter circuit, which result in increases of a chip size and a manufacturing cost.
On the other hand, the MOS transistor is characterized in that a drain current having a component in proportion to square of an input voltage between a gate and a source is output. Assuming that the voltage between the gate and the source is represented by Vgs and a threshold voltage is represented by Vth, the drain current Id is given by the following equation: EQU Id=K(Vgs-Vth).sup.2 (1)
where K is a constant in relation to a gate length and width (see "Ultrafast MOS device edited by Koyama Shin, Baifu kan, Tokyo, page 8). PA1 a first MIS transistor having a gate to which a first input signal is applied; PA1 a second MIS transistor having a gate to which a second input signal is applied and having substantially the same current driving ability as that of the first MIS transistor; PA1 a third MIS transistor having a gate to which a signal obtained by adding the first input signal and the second input signal is applied; and PA1 an adding-subtracting circuit for adding a drain current of the first MIS transistor and a drain current of the second MIS transistor to obtain an addition result, subtracting a current corresponding to a substantially two-fold drain current of that of the first MIS transistor from the addition result on the basis of a drain current of the third MIS transistor, and outputting a subtraction result, PA1 wherein when a signal obtained by superimposing a first AC signal to a first DC voltage is supplied as the first input signal, and a signal obtained by superimposing a second AC signal having the same absolute value peak voltage as the first AC signal and a reversed phase of the first AC signal to a second DC voltage having the approximately same voltage as the first DC voltage is supplied as the second input signal, a squared signal of the first AC signal of the first input signal is output as the subtracting result from the adding-subtracting circuit. PA1 a first MIS transistor having a gate to which a first input signal is applied, and having a channel of a first conductivity type; PA1 a second MIS transistor having a gate to which a second input signal is applied, having a channel of the first conductivity type and having substantially the same current driving ability as that of the first MIS transistor; PA1 a third MIS transistor having a gate to which a signal obtained by adding the first input signal to the second input signal is applied, and having a channel of the first conductivity type; PA1 an adding-subtracting circuit for adding a first drain current of the first MIS transistor and a second drain current of the second MIS transistor to obtain an addition result, subtracting a current corresponding to a substantially tow-fold drain current of that of the first MIS transistor from the addition result, based on a third drain current of the third MIS transistor, and outputting a subtraction result; and PA1 an output terminal to which the subtraction result of the adding-subtracting circuit is output, PA1 wherein each source of the first, the second and the third MIS transistors is connected to a first power supply potential and the adding-subtracting circuit includes fourth and fifth MIS transistors each having a channel of a second conductivity type, and each source of the fourth and the fifth MIS transistor is connected to a second power supply potential, gates of the fourth and the fifth MIS transistors are connected in common to a drain of the fifth MIS transistor, the drain of the fifth MIS transistor is connected to a drain of the third MIS transistors, and a drain of the fourth MIS transistor is connected to drains of the first and the second MIS transistors and the output terminal.
However, as is apparent from the equation (1), the output current Id includes a component associated with the threshold voltage Vth. Therefore, the output current is largely distorted.
In the method in which a squared alternating-current signal is obtained by using the formula (1), an element associated with the threshold voltage is included. As a result, only a signal largely distorted is obtained.